The simultaneous multi-threading (SMT) technique adopted in a Power5 (registered trademark) processor made by IBM Corporation causes a single processor to execute two threads simultaneously, provides the threads in execution with priorities, and thereby enables variation of a proportion of processor resources used by the threads which are simultaneously executed (see R. Kalla, B. Sinharoy, and J. Tendler, “Simultaneous Multi-threading Implementation in POWER5—IBM's Next Generation POWER Microprocessor,” A symposium on High Performance Chips, with URL:                http://www.            followed by: hotchips.org/    followed by: archive/hc15/pdf/    followed by: 11.ibm.pdf)(hereinafter referred to as “Non-patent Literature 5”). In other words, two logical processors existing on a single actual processor changes computational capabilities thereof depending on the priorities of the threads to be executed. Therefore, in the Power5 processor, it is essential to balance the computational capabilities of the two logical processors existing on the single actual processor and thereby to achieve a high execution performance.
For example, in order to achieve the high execution performance in a program area having high instruction-level parallelism, the processor needs to contain large computational resources. On the contrary, in a program area having low instruction-level parallelism, even a processor containing small computational resources can achieve sufficient performances. Meanwhile, a Pentium (registered trademark) M processor is configured to change the computational capability thereof by shifting an operating frequency instead of using the thread priorities (see “Intel® Pentium® M Processor Datasheet,” Document Number: 252612-003, April 2004) (hereinafter referred to as “Non-patent Literature 3”). For example, in a program area where cache misses occur frequently and the processor becomes idle frequently, an increase in execution time is very limited even when the operating frequency is reduced. Accordingly, it is possible to reduce energy consumption in a large amount.
The above-described processor, which is able to change the computational capabilities, can reduce the energy consumption without sacrificing execution speed by means of analyzing characteristics of program codes and extracting a program area in which the increase in execution time is not caused while the computational capabilities is reduced. For example, there has been proposed a technique using a processor configured to shift the operating frequency dynamically, in which execution time for each program area is measured, while an operating frequency is shifted, to obtain the operating frequency which can suppress a proportion of increases in the execution time for respective program areas below a threshold (see C. H. Hsu and U. Kremer, “The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction,” PLDI, 2003)(hereinafter referred to as “Non-patent Literature 1”).
However, in the technique disclosed in Non-patent Literature 1, measurement of the execution time is carried out by profiling (offline profiling) test execution using test data. That is, the computational capabilities given to the respective program areas are not changed during the program is actually in execution instead of during the test execution. For this reason, when characteristics of input data vary in the course of executing the program, it is not possible to adjust a computational capability of a central processing unit so as to follow such variation.
Moreover, the above-described threshold is a constant. Accordingly, if the computational capability is reduced based on this threshold, there is a risk of an increase in the energy consumption as a consequence. For example, when power consumption (Watts) is reduced from Wi to Wi-1 due to reduction in the computational capability and the execution time is increased from Ti to Ti-1, the energy consumption (Joule) is changed from Wi×Ti to Wi-1×Ti-1. However, in the case where the increase in the execution time is great relative to reduction in the power consumption even if a proportion of increase in the execution time is equal to or smaller than the above-described threshold, Wi×Ti may become smaller than Wi-1×Ti-1 and the energy consumption may therefore be increased.